Dojo

Tesla Publishes 'Wafer alignment structure' Patent for Dojo Supercomputer

Tesla Publishes 'Wafer alignment structure' Patent for Dojo Supercomputer

Image: Tesla Patent

Tesla continues to make progress in the development of neural network (NN) chips to increase the learning rate of server-side neural networks. The new patent, ‘Wafer alignment structure,’ improves the microarchitecture of Dojo tiles.

At Tesla AI Day, which took place in 2021, the company unveiled its Dojo supercomputing technology. Dojo's goal is to increase the speed and accuracy of training. Dojo is a Neural Network (NN) chip being developed by Tesla's hardware team to increase the learning speed of neural networks on the server side. The company showed the Dojo D1 chip, which uses 7nm technology and delivers breakthrough bandwidth and computing performance.

To house the chips, the company has developed what it calls 'training tiles' with which to build its computing systems. Each tile consists of 25 D1 chips in an integrated multi-chip module, with each tile providing nine petaflops of computing and 36tbps of off-tile bandwidth. Each of the D1 chips consists of several layers, which are made of different materials.

Precise alignment of an element to another element at the wafer level can be challenging. In a system, such as a system on a wafer assembly, a high coefficient of thermal expansion (CTE) element and a low CTE element can be mounted to one another. For example, a system on a wafer and a heat dissipation structure can have different CTEs and be attached to each other. A mismatch between the CTEs of the elements causes misalignment between the elements due to thermal stress.

To solve this problem, Tesla developed the wafer level alignment structure, which it patented. The company filed a patent for “Wafer alignment structure” on February 23, 2022, and published it on September 9, 2022. It claims the benefit of the U.S. Provisional Patent Application titled “WAFER ALIGNMENT STRUCTURE,” filed March 1, 2021.

In fact, the invention relates to the proper arrangement and fixation of the wafers in the chip, which will allow it to hold together regardless of the micro-movements associated with a change in the size of one or more components caused by heating or cooling. In addition, the use of a material that has a coefficient of thermal expansion that is lower than a coefficient of thermal expansion of a material of the element is also considered.

© 2022, Eva Fox | Tesmanian. All rights reserved.

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Article edited by @SmokeyShorts; follow him on Twitter

About the Author

Eva Fox

Eva Fox

Eva Fox joined Tesmanian in 2019 to cover breaking news as an automotive journalist. The main topics that she covers are clean energy and electric vehicles. As a journalist, Eva is specialized in Tesla and topics related to the work and development of the company.

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